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Western Digital's New Solutions to Support RISC-V Ecosystem
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Western Digital Corporation (WDC - Free Report) unveiled three latest open-source innovations at the RISC-V Summit at Santa Clara, CA. The company also announced that it is making progress toward transitioning approximately one billion of its processor cores to RISC-V’s standard architecture.
The company’s intention to open source its newly developed RISC-V standard SweRV Core was the key takeaway at the summit. With this move, the company attempts to accelerate the development of emerging data-centric technologies including the likes ofsecure processing, connected applications, Internet of Things (“IoT”), industrial controls, among others.
The latest RISC-V SweRV core is anticipated to accelerate the development process of customized design architecture “from core to edge.”
The core which has a 2-way design is expected to be made available in the first quarter of 2019. The new “32-bit, 9 stage pipeline” core is estimated to runat 4.9 CoreMarks/Mhz (megahertz). It provides clock speeds of up to 1.8gigahertz (Ghz), per company estimates on a 28mm CMOS (Complementary metal–oxide–semiconductor) process technology.
Western Digital expects the latest core to find application in the company’s diverse internal embedded designs, comprising SSDsand flash controllers.
Western Digital also unveiled OmniXtend and SweRV Instruction Set Simulator (“ISS”). OmniXtend, an open solution, offers cache coherent memory to facilitate data sharing and access across processors. The new approach which currently supports Ethernet fabric is expected to run on other advanced fabrics, going ahead.
SweRV ISS provides “full test bench support” on RISC-V core architecture. Per the press release , "An ISS is a computer program, simulates the execution of instructions of a processor.”
In fact, Western Digital leveraged SweRV ISS to meticulously authenticate and simulate the latest SweRV Core, having executed instructions exceeding 10 billion. Both OmniXtend and SweRV ISS are available for download.
The company envisions SweRV ISS and SweRV Core to drive the industry’s transition to an open source and scalable instruction set architecture.
Open Source Approach: A Key Catalyst
Open source hardware, touted as the next big thing, is anticipated to revolutionize the processor market. This new trend is expected to democratize processor design.RISC-V is a free open source and scalable instruction set architecture based on RISC (Reduced Instruction Set Computing) principles, paving the way for processor innovation.
The processor innovations are anticipated to drive the development of customized compute architectures. These robust innovations are eventually expected to facilitate workloads seamlessly, across data centers, mobile systems and industrial device controllers, among other Fast Data and Big Data environments.
Endpoint and edge computing call for a flexible architecture that enables heavy application workloads to run efficiently. In this new age computing era, configurability and power efficiency turn out to be the decisive factors edging out traditional speed count, feeds and other metrics.
Consequently, RISC-V becomes a cost-effective (as it is freely accessible) alternative approach to otherwise purpose-specific compute architectures. Additionally, the RISC-V open standard architectures are expected to find utilization in supporting other applications including the likes of memory centric solutions, unique storage, flexible interconnect specialty processing and applications.
RISC-V ecosystem has gained acknowledgment from notable technology players including the likes of NVIDIA (NVDA - Free Report) , Microchip (MCHP - Free Report) , Mellanox , Micron, to name a few.
To Conclude
Embracing the innovative trend in the processor market is a positive move. We believe the latest development holds potential and is likely to revive Western Digital’s client devices segment in the long term.
Notably, in the first-quarter of fiscal 2019, client devices revenues (52.7% of total revenues) declined roughly 1% year over year and came in at $2.65 billion, primarily owing to sluggishness in client compute hard drives.
However, stiff competition from Seagate, Hitachi, Samsung and Intel in the storage and pricing pressure add to woes. Customer concentration also remains a headwind. Softness in flash market pricing trends remains a headwind in the near-term.
Western Digital carries a Zacks Rank #5 (Strong Sell).
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Western Digital's New Solutions to Support RISC-V Ecosystem
Western Digital Corporation (WDC - Free Report) unveiled three latest open-source innovations at the RISC-V Summit at Santa Clara, CA. The company also announced that it is making progress toward transitioning approximately one billion of its processor cores to RISC-V’s standard architecture.
The company’s intention to open source its newly developed RISC-V standard SweRV Core was the key takeaway at the summit. With this move, the company attempts to accelerate the development of emerging data-centric technologies including the likes ofsecure processing, connected applications, Internet of Things (“IoT”), industrial controls, among others.
The latest RISC-V SweRV core is anticipated to accelerate the development process of customized design architecture “from core to edge.”
The core which has a 2-way design is expected to be made available in the first quarter of 2019. The new “32-bit, 9 stage pipeline” core is estimated to runat 4.9 CoreMarks/Mhz (megahertz). It provides clock speeds of up to 1.8gigahertz (Ghz), per company estimates on a 28mm CMOS (Complementary metal–oxide–semiconductor) process technology.
Western Digital expects the latest core to find application in the company’s diverse internal embedded designs, comprising SSDsand flash controllers.
Western Digital also unveiled OmniXtend and SweRV Instruction Set Simulator (“ISS”). OmniXtend, an open solution, offers cache coherent memory to facilitate data sharing and access across processors. The new approach which currently supports Ethernet fabric is expected to run on other advanced fabrics, going ahead.
SweRV ISS provides “full test bench support” on RISC-V core architecture. Per the press release , "An ISS is a computer program, simulates the execution of instructions of a processor.”
In fact, Western Digital leveraged SweRV ISS to meticulously authenticate and simulate the latest SweRV Core, having executed instructions exceeding 10 billion. Both OmniXtend and SweRV ISS are available for download.
Western Digital Corporation Price and Consensus
Western Digital Corporation Price and Consensus | Western Digital Corporation Quote
The company envisions SweRV ISS and SweRV Core to drive the industry’s transition to an open source and scalable instruction set architecture.
Open Source Approach: A Key Catalyst
Open source hardware, touted as the next big thing, is anticipated to revolutionize the processor market. This new trend is expected to democratize processor design.RISC-V is a free open source and scalable instruction set architecture based on RISC (Reduced Instruction Set Computing) principles, paving the way for processor innovation.
The processor innovations are anticipated to drive the development of customized compute architectures. These robust innovations are eventually expected to facilitate workloads seamlessly, across data centers, mobile systems and industrial device controllers, among other Fast Data and Big Data environments.
Endpoint and edge computing call for a flexible architecture that enables heavy application workloads to run efficiently. In this new age computing era, configurability and power efficiency turn out to be the decisive factors edging out traditional speed count, feeds and other metrics.
Consequently, RISC-V becomes a cost-effective (as it is freely accessible) alternative approach to otherwise purpose-specific compute architectures. Additionally, the RISC-V open standard architectures are expected to find utilization in supporting other applications including the likes of memory centric solutions, unique storage, flexible interconnect specialty processing and applications.
RISC-V ecosystem has gained acknowledgment from notable technology players including the likes of NVIDIA (NVDA - Free Report) , Microchip (MCHP - Free Report) , Mellanox , Micron, to name a few.
To Conclude
Embracing the innovative trend in the processor market is a positive move. We believe the latest development holds potential and is likely to revive Western Digital’s client devices segment in the long term.
Notably, in the first-quarter of fiscal 2019, client devices revenues (52.7% of total revenues) declined roughly 1% year over year and came in at $2.65 billion, primarily owing to sluggishness in client compute hard drives.
However, stiff competition from Seagate, Hitachi, Samsung and Intel in the storage and pricing pressure add to woes. Customer concentration also remains a headwind. Softness in flash market pricing trends remains a headwind in the near-term.
Western Digital carries a Zacks Rank #5 (Strong Sell).
You can see the complete list of today’s Zacks #1 Rank (Strong Buy) stocks here.
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